ADRs tagged gpu¶
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95 ADR(s) carry this tag.
| ID | Title |
|---|---|
| ADR-0101 | SYCL USM-backed picture pre-allocation pool |
| ADR-0127 | Vulkan compute backend — vendor-neutral GPU path alongside CUDA/SYCL/HIP |
| ADR-0175 | Vulkan compute backend — scaffold-only audit-first PR (T5-1) |
| ADR-0176 | Vulkan VIF cross-backend gate (lavapipe + Arc nightly) |
| ADR-0177 | Vulkan motion kernel + motion cross-backend gate |
| ADR-0178 | Vulkan ADM kernel (T5-1c-adm) |
| ADR-0181 | Global feature-characteristics registry + per-backend dispatch strategy |
| ADR-0182 | GPU long-tail batch 1 — psnr + ciede + moment on CUDA / SYCL / Vulkan |
| ADR-0187 | ciede2000 Vulkan kernel — float-precision per-pixel ΔE |
| ADR-0188 | GPU long-tail batch 2 — psnr_hvs / ssim / ms_ssim across CUDA / SYCL / Vulkan |
| ADR-0189 | float_ssim Vulkan kernel — host decimation, 2-dispatch GPU |
| ADR-0190 | float_ms_ssim Vulkan kernel — 5-level pyramid + Wang product on host |
| ADR-0191 | float_psnr_hvs Vulkan kernel — overlapping 8×8 DCT blocks + per-plane log transform |
| ADR-0192 | GPU long-tail batch 3 — closing every remaining metric gap (motion_v2 / float_ansnr / ssimulacra2 / cambi + float twins) |
| ADR-0193 | motion_v2 Vulkan kernel — single-dispatch SAD via convolution linearity |
| ADR-0194 | float_ansnr GPU kernels — single-dispatch 3x3 + 5x5 filters with per-WG float partials |
| ADR-0195 | float_psnr GPU kernels — single-dispatch diff² with float partials, bit-exact vs CPU |
| ADR-0196 | float_motion GPU kernels — float twin of integer_motion blur+SAD |
| ADR-0197 | float_vif GPU kernels — 4-scale pyramid with mirror-asymmetry fix |
| ADR-0199 | float_adm Vulkan kernel — sixth Group B float twin |
| ADR-0201 | ssimulacra2 Vulkan kernel |
| ADR-0202 | float_adm CUDA + SYCL twins — sixth Group B float kernel finishes |
| ADR-0205 | cambi GPU feasibility spike |
| ADR-0206 | ssimulacra2 CUDA + SYCL twins |
| ADR-0210 | cambi Vulkan integration (Strategy II hybrid) |
| ADR-0212 | HIP (AMD ROCm) compute backend — scaffold-only audit-first PR (T7-10) |
| ADR-0214 | GPU-parity CI gate (T6-8) — cross-device variance matrix |
| ADR-0216 | Vulkan PSNR — chroma extension (psnr_cb / psnr_cr) |
| ADR-0219 | motion3 GPU coverage on Vulkan + CUDA + SYCL (3-frame window) |
| ADR-0220 | SYCL feature kernels are unconditionally fp64-free |
| ADR-0234 | GPU-generation-aware ULP calibration head |
| ADR-0239 | Backend-agnostic GPU picture pool (gpu_picture_pool.{h,c}) |
| ADR-0240 | GPU backend public-header pattern doc (PR3 of GPU dedup, doc-only) |
| ADR-0241 | HIP first-consumer kernel — integer_psnr_hip via mirrored kernel-template |
| ADR-0243 | enable_lcs MS-SSIM extras on CUDA + Vulkan |
| ADR-0246 | Per-backend GPU kernel scaffolding templates (CUDA + Vulkan) |
| ADR-0254 | HIP second-consumer kernel — float_psnr_hip via mirrored kernel-template |
| ADR-0259 | HIP third-consumer kernel — ciede_hip via mirrored kernel-template |
| ADR-0260 | HIP fourth-consumer kernel — float_moment_hip via mirrored kernel-template |
| ADR-0266 | HIP fifth kernel-template consumer — float_ansnr_hip |
| ADR-0267 | HIP sixth kernel-template consumer — motion_v2_hip |
| ADR-0271 | Wire integer_ms_ssim_cuda through the CUDA fence-batching helper |
| ADR-0273 | HIP seventh kernel-template consumer — float_motion_hip |
| ADR-0274 | HIP eighth kernel-template consumer — float_ssim_hip |
| ADR-0290 | NVENC codec adapters for vmaf-tune (h264 / hevc / av1) |
| ADR-0314 | vmaf-tune --score-backend=vulkan (vendor-neutral GPU scoring) |
| ADR-0315 | Vendor-neutral VVC encode strategy — tiered Tier-1-now / Tier-2-backlog / Tier-3-revisit |
| ADR-0338 | macOS Vulkan-via-MoltenVK CI lane (advisory) for the Vulkan backend |
| ADR-0345 | cambi × {CUDA, SYCL, HIP} GPU port strategy |
| ADR-0351 | CUDA PSNR — chroma extension (psnr_cb / psnr_cr) |
| ADR-0353 | Vulkan submit-pool migration PR-B — six secondary kernels |
| ADR-0356 | Two-level GPU reduction for Vulkan VIF / ADM / motion accumulators |
| ADR-0360 | CAMBI CUDA port (Strategy II hybrid, T3-15a) |
| ADR-0361 | Metal compute backend — scaffold-only audit-first PR (T8-1) |
| ADR-0372 | HIP Batch-1 — integer_psnr_hip and float_ansnr_hip Real Kernels |
| ADR-0373 | HIP Batch-2 — float_motion_hip Real Kernel |
| ADR-0375 | HIP batch-3 — float_moment_hip and float_ssim_hip real kernels |
| ADR-0376 | Fix silent error-swallow in Vulkan buffer-invalidate readback functions |
| ADR-0377 | HIP batch-4 — ciede_hip and integer_motion_v2_hip real kernels |
| ADR-0378 | Per-picture CUDA streams must use CU_STREAM_NON_BLOCKING |
| ADR-0385 | Feature-extractor deduplication by provided-feature names |
| ADR-0391 | ciede2000 Vulkan NVIDIA places=4 fork debt is a structural f32/f64 precision gap |
| ADR-0410 | ssimulacra2_cuda GPU module leak + per-scale malloc removal |
| ADR-0415 | CAMBI SYCL port — closes last CUDA-to-SYCL parity gap |
| ADR-0420 | Metal backend runtime (T8-1b) |
| ADR-0421 | Metal first kernel — integer_motion_v2 (T8-1c) |
| ADR-0422 | CLI HIP and Metal Backend Selectors |
| ADR-0423 | Metal IOSurface zero-copy import (T8-IOS) |
| ADR-0445 | Persistent VkPipelineCache for Vulkan compute backend |
| ADR-0451 | Local dev-MCP container for live probing |
| ADR-0454 | VIF CUDA shared-memory staging for horizontal and vertical filter passes |
| ADR-0458 | SYCL CAMBI queue-sync collapse + SSIM horizontal SLM staging |
| ADR-0464 | CAMBI CUDA spatial-mask shared-memory tile |
| ADR-0484 | Extend kernel-scaffolding.md with HIP and Metal lifecycle contract |
| ADR-0486 | Codify the three-function GPU backend context-API contract in docs |
| ADR-0488 | Shared once-snapshot helper for GPU dispatch env variables |
| ADR-0489 | CAMBI SYCL — Replace GPU-to-GPU q.wait() Calls with Event Chains (SY-1) |
| ADR-0514 | dev-MCP container exposes every host GPU backend (CUDA + SYCL + Vulkan + HIP) |
| ADR-0519 | Implement vmaf_hip_import_state to unblock --backend hip |
| ADR-0523 | Register vmaf_fex_integer_motion_hip in the extractor list |
| ADR-0530 | HIP feature-extractor flag promotion and HIP_DEVICE picture-buffer type |
| ADR-0533 | Full HIP feature-extractor registration sweep |
| ADR-0537 | HIP integer VIF kernel crash fix — filter upload, bounds, HtoD staging |
| ADR-0539 | integer ADM HIP kernels — real implementation replacing weak HSACO stubs |
| ADR-0541 | Pin dev-MCP container Intel NEO + ROCm runtimes to versions matching the host kernel |
| ADR-0552 | Deterministic wavefront reduction for integer_vif_hip horizontal kernels |
| ADR-0563 | HIP extractor audit — verification of 9 remaining scaffold claims |
| ADR-0564 | Real integer_ssim GPU kernels (CUDA, HIP, SYCL) — replace silent float_ssim substitution |
| ADR-0567 | Real On-Device GPU Kernels for speed_chroma and speed_temporal (4 Backends) |
| ADR-0568 | Default sycl_icpx_aot_targets to full Intel arch list |
| ADR-0587 | Real Metal Compute Kernels for CAMBI |
| ADR-0593 | HIP integer_moment kernel — register real HSACO blob alongside psnr / psnr_hvs |
| ADR-0667 | vmaf-tune score backend native priority |
| ADR-0699 | VMAFX Helm Chart and Kubernetes Manifests with 3-Vendor GPU Device-Plugin Support |
| ADR-0726 | Drop Vulkan backend |